A selective epitaxial growth method (hereinafter, referred to as SEG) of partitioning an epitaxial growth region on a single crystal substrate, for example, a silicon single crystal substrate, by a growth suppression film such as a silicon oxide film to selectively grow an epitaxial layer on the epitaxial growth region is known. A typical SEG method is described in a related art.
As is also described in the related art, in the SEG, for example, supply of a silicon source gas and supply of an etching gas are alternately repeated. That is, the silicon epitaxial layer is selectively grown on the epitaxial growth region, while repeating an epitaxial growth of silicon and etching of extra silicon deposited on an interlayer insulating film including the growth suppression film, for example, a silicon oxide film.
The SEG has been applied to a relatively wide shallow region (an aspect ratio of less than “1”) like a so-called elevated source/drain structure which is obtained by selectively growing silicon, for example, on a source and drain region of MOSFET in a manufacturing process of a semiconductor integrated circuit device. However, recently, an application of the SEG to a relatively narrow and deep region (an aspect ratio of “1” or more), for example, burying a hole pattern, or a space pattern of line and space patterns has also been considered.
High integration of the semiconductor integrated circuit device still continues to progress. Therefore, in the hole pattern or the space pattern, a dimension in a plane direction tends to become narrower, and a dimension in a depth direction tends to become deeper. The aforementioned pattern is a so-called high aspect ratio of the hole pattern or the space pattern.
The burying of the hole pattern or the space pattern having such a high aspect ratio using the SEG requires a long processing time. The reason is that it is necessary to increase the number of repetitions of the epitaxial growth of silicon and etching of extra silicon. Therefore, degradation of throughput is inevitable when manufacturing the semiconductor integrated circuit device.
In order to solve the degradation of the throughput, it is conceivable to increase a growth rate of the silicon during its epitaxial growth. The increase in growth rate prevents an increase in processing time, even in burying the hole pattern or the space pattern having the high aspect ratio.
However, a problem occurs when changes in processing conditions such as a processing pressure during the epitaxial growth for the purpose of an increase in the growth rate. In these instances, crystalline orientation of a grown silicon epitaxial layer or a surface flatness thereof may degrade.